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copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. 3mhz synchronous switch-mode battery charger with full usb compli- ance and usb-otg boost regulator features general description charge faster than linear charger 3mhz with 0% to 99.5% duty cycle synchronous switch-mode charger with 1.5a integrated n- mosfets 4v-6v input operating range 20v absolute maximum input voltage safety -reverse leakage protection to prevent battery drainage -thermal regulation and protection -input/output over-voltage protection -cycle-by-cycle current limit accuracy -+ 1% charge voltage regulation (0 to 85 o c) -+ 5% charge current regulation -+ 5% input current regulation (100ma and 500ma) built-in input current sensing and limiting automatic charging programmable through high-speed i 2 c interface(3.4mb/s) -input current limit -fast-charge and termination current -charge regulation voltage -weak battery voltage threshold -vin dpm threshold -termination enable/disable -otg enable/disable -reset all parameter control -safety timer with reset control 5v, 500ma boost mode for usb otg for 2.5v to 4.5v battery input the apw7262 combine switch-mode battery charger and a boost regulator with fixed 3mhz switching frequency, which drives two integrated n-channel power mosfets. in battery charging, the high-efficiency step-down dc/dc converter is capable of delivering 1.5a output current over a wide input voltage range from 4v to 6v for apw7262, the step-down dc/dc converter is ideally suited for portable electronic devices that are powered from 1-cell li-ion battery. the charging parameters and operating modes can be programmed through an i 2 c interface. the apw7262 has high accuracy regulation of input current, charge current and charge voltage. it equipped with charge termination, and charge status monitoring for battery detection. the apw7262 charge the battery in three phases: conditioning, constant current and constant voltage. the apw7262 features dynamic power management (dpm) mode to accomplish input power limiting. the input cur- rent is limited to the value set by the i 2 c host. this feature reduces battery charge current when the input power limit is reached to avoid overloading the ac adapter when sup- plying the load and the battery charger simultaneously. the charge termination is based on battery voltage, a programmed minimum current level and charge current termination bit set by the i 2 c host. if the battery voltage falls below an internal threshold, the apw7262 automatically restarts the charge cycle, and when the input voltage falls below the battery voltage, it will enter a low-quiescent current sleep mode. the apw7262 supports the thermal regulation and over tem- perature protection to maintain the junction temperature of 120 o c by reducing charge current. the apw7262 can operate as a boost regulator. to sup- port usb otg device, apw7262 can provide vbus (5.05v) by boosting the battery voltage. the apw7262 is available in1.7mmx2.1mm wlcsp-20 and tqfn4x4-20a packages. available in 1.7mmx2.1mm wlcsp-20 and tqfn4x4-20a packages
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 2 applications cell phones, smart phones and pdas tablet pc portable media players, handheld device simplified application circuit ordering and marking information note: anpec lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with rohs. anpec lead-free products meet or exceed the lead-free requirements of ipc/jedec j - std-020d for msl classification at lead-free peak reflow temperature. anpec defines green to mean lead-free (rohs compliant) and halogen free (br or cl does not exceed 900ppm by weight in homogeneous material and total of br and cl does not exceed 1500ppm by weight). vbus pgnd csin sw boot vbat adapter or usb r sns pmid sda scl otg cd stat vaux csout 10k 10k 10k c vbus c pmid l out c boot c sin c sns pack+ pack- c out1 to system c out2 apw7262 c sout regn c pmid package code ha : wlcsp1.7x2.1-20 qb : tqfn4x4-20a operating ambient temperature range i : -40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device apw7262 handling code temperature range package code assembly material apw7262ha: x - date code 7262 ? x apw7262qb: x - date code apw 7262 xxxxx ?
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 3 pin configuration absolute maximum ratings (note 1,2) note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability note 2: the device is esd sensitive. handling precautions are recommended. thermal characteristics (note 3) symbol parameter typical value unit wlcsp1.7x2.1-20 85 q ja junction-to-ambient resistance in free air tqfn4x4-20a 41 o c/w wlcsp1.7x2.1-20 25 q jc junction-to-case resistance in free air tqfn4x4-20a 9 o c/w symbol parameter rating unit vbus, pmid and stat to pgnd voltage -0.3 to 20 v boot and sw to pgnd voltage -0.3 to 20 v v i/o scl, sda, otg, regn, csin, csout and cd to pgnd voltage -0.3 to 7 v v boot boot supply voltage (boot to sw) -0.3 ~ 7 v t j maximum junction temperature 150 o c t stg storage temperature -65 to 150 o c t sdr maximum lead soldering temperature (10 seconds) 260 o c note 3: q ja is measured with the component mounted on a high effective the thermal conductivity test board in free air. apw7262 top view boot (a3) pmid (b3) sw (c3) vbus (a2) pmid (b2) sw (c2) vbus (a1) pmid (b1) sw (c1) scl (a4) sda (b4) stat (c4) pgnd (d3) regn (e3) pgnd (d2) cd (e2) pgnd (d1) csin (e1) otg (d4) csout (e4) 1.7x2.1mm 20-pin wlcsp-20 s d a s c l nc vbus p g n d p m i d s w csin nc o t g s t a t nc boot vbus s w p m i d gnd cd regn 21 gnd 14 13 12 11 15 2 3 4 5 1 19 181716 20 7 8 9 10 6 c s o u t = thermal pad (connected to gnd plane for better heat dissipation) tqfn4x4-20 (top view)
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 4 symbol parameter range unit v bus supply voltage (vbus to gnd) 4 to 6 v v out converter output voltage 3.5 to 4.44 v i out output current (r sns =68 m ) 0.55~1.55 a t a ambient temperature -40 to 85 o c t j junction temperature -40 to 125 o c recommended operating conditions (note 4) note 4: refer to the typical application circuit. electrical characteristics apw7262 symbol parameter test conditions min typ max unit input current i vbus vbus supply current control v bus > v bus(min) , pwm switching - 10 - ma v bus > v bus(min) , pwm no switching - - 5 ma 0 o c < t j < 85 o c, cd=1 or hz_mode=1 - 140 260 m a i lkg leakage current from battery to vbus pin 0 o c < t j < 85 o c, v csout =4.2v, high impedance mode, v bus =0v - 0.2 5 m a battery discharge current in high impedance mode, (csin, csout, sw pins) 0 o c < t j < 85 o c, v csout =4.2v, high impedance mode, scl, sda, otg=0v or 1.8v - - 20 m a voltage regulation v oreg output regulation voltage programmable range operating in voltage regulation 3.5 - 4.44 v t a = 25 o c -0.5 - 0.5 voltage regulation accuracy t a = -40 ~ 85 o c -1 - 1 % current regulation (fast charge) i o(charge) output charge current programmable range v lowv Q v csout v slp , r sns =68m w , low_chg=0 550 - 1500 ma low charge current v lowv Q v csout v slp , r sns =68m w , low_chg=1 - 325 350 ma 20mv < v ireg < 40mv -8 - 2 % charge current accuracy across r sns 40mv < v ireg -6 - 0 % 37.4mv Q v ireg <44.2mv -3.5 - 3.5 regulation accuracy of the voltage across r sns (for charge current regulation) v ireg = i o(charge) x r sns 44.2mv Q v ireg -3 - 3 % weak battery detection v lowv weak battery voltage threshold programmable range adjustable using i 2 c control 3.4 - 3.7 v weak battery voltage accuracy -5 - 5 % hysteresis for v lowv battery voltage falling - 100 - mv deglitch time for weak battery threshold rising voltage, 2mv overdrive, t rise =100ns - 30 - ms unless otherwise specified, these specifications apply over v bus =5v, cd=0, hz_mode=0, opa_mode=0 and t a = -40 to 85 o c. typical values are at t a =25 o c.
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 5 electrical characteristics apw7262 symbol parameter test conditions min typ max unit cd and otg pin logic level v il input low threshold level - - 0.4 v v ih input high threshold level 1.5 - - v i bias input bias current voltage on control pin is 5v - - 1 m a charge termination detection i term termination charge current programmable range v csout >v oreg -v regh , v bus >v slp , r sns =68m w 50 - 400 ma deglitch time for charge termination both rising and falling, 2mv overdrive, t rise , t fal l=100ns - 30 - ms 3.4mv Q v ireg_term Q 6.8mv -25 - 25 6.8mv Q v ireg_term Q 17mv -25 - 25 regulation accuracy for termination current across rsns v ireg_term =i oterm x r sns 17mv Q v ireg_term Q 27.2mv -5 - 5 % input based dynamic power management v in_dpm input voltage dpm threshold programmable range 4.2 - 4.76 v vin dpm threshold accuracy -3 - 3 % input current limit t j =0 o c~125 o c 88 93 98 i in =100ma t j =-40 o c ~125 o c 86 93 98 t j =0 o c ~125 o c 450 475 500 i in_limit input current limiting threshold i in =500ma t j =-40 o c ~125 o c 440 475 500 ma vref bias regulator v regn input bias regulator voltage v bus >v in(min) or v csout >v bus(min) , i regn =1ma, c regn =1 m f - - 6.5 v v regn output short current limit - 30 - ma battery recharge threshold v rch recharge threshold voltage below v oreg - 120 - mv deglitch time v csout decreasing below threshold, t fall =100ns, 10mv overdrive - 130 - ms stat output low-level output saturation voltage, stat pin i o =10ma, sink current - - 0.55 v v ol(stat) high-level leakage current for stat voltage on stat pin is 5v - - 1 m a i 2 c bus logic levels and timing characteristic v ol output low threshold level i o =10ma, sink current - - 0.4 v v il input low threshold level v pull_up =1.8v, sda and scl - 0.4 v v ih input high threshold level v pull_up =1.8v, sda and scl 1.2 - - v i bias input bias current v pull_up =1.8v, sda and scl - - 1 m a f scl scl clock frequency v pull_up =1.8v, sda and scl - - 3.4 mhz unless otherwise specified, these specifications apply over v bus =5v, cd=0, hz_mode=0, opa_mode=0 and t a = -40 to 85 o c. typical values are at t a =25 o c.
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 6 electrical characteristics apw7262 symbol parameter test conditions min typ max unit battery detection (in termination) i detect battery detection current before charge done (sink current) begins after termination detected, v csout Q v oreg - -0.8 - ma t detect battery detection time - 262 - ms sleep comparator v slp sleep mode entry threshold, v bus -v csout 2.3v Q v csout Q v oreg , v bus falling 0 40 100 mv v slp_exit sleep mode exit hysteresis 2.3v Q v csout Q v oreg 140 200 260 mv deglitch time for v bus rising above v slp +v slp_exit rising voltage, 2mv overdrive, t rise =100ns - 30 - ms undervoltage lockout (uvlo) uvlo ic active threshold voltage v bus rising, exit uvlo 3.6 3.8 4 v uvlo_hys ic active hysteresis v bus falling below uvlo, enter uvlo - 150 - mv pwm i in_limit =500ma, measured from vbus to pmid (for wlcsp-20) - 180 250 internal top reverse blocking mosfet on-resistance i in_limit =500ma, measured from vbus to pmid (for tqfn-20a) - 220 290 measured from pmid to sw, v boot -v sw =4v (for wlcsp-20) - 130 225 m w internal top n-channel switching mosfet on-resistance measured from pmid to sw, v boot -v sw =4v (for tqfn-20a) - 170 265 measured from sw to pgnd (for wlcsp-20) - 130 225 internal bottom n- channel mosfet on-resistance measured from sw to pgnd (for tqfn-20a) - 170 265 f osc oscillator frequency 2.7 3 3.3 mhz charge mode protection input vbus ovp threshold voltage v bus threshold to turn off converter during charge v ovp_in_usb 6.3 6.5 6.7 v v ovp_in_usb v ovp_in_usb hysteresis vbus falling from above v ovp_in_usb - 170 - mv v ovp output ovp threshold voltage v csout threshold over v oreg to turn off charger during charge 110 117 121 % v ovp hysteresis lower limit for v csout falling from above v ovp - 11 - % i ilimit cycle-by-cycle current limit for charge charge mode operation 2.4 3 3.5 a trickle to fast charge threshold v csout rising 1.9 2.1 2.3 v v short v short hysteresis v csout falling below v short - 100 - mv unless otherwise specified, these specifications apply over v bus =5v, cd=0, hz_mode=0, opa_mode=0 and t a = -40 to 85 o c. typical values are at t a =25 o c.
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 7 electrical characteristics apw7262 symbol parameter test conditions min typ max unit charge mode protection i short trickle charge charging current v csout Q v short 25 35 45 ma boost mode operation for vbus (opa_mode=1, hz_mode=0) v bus_b boost output voltage (to vbus pin) 2.5v copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 8 i 2 c serial control port operation apw7262 symbol parameter test conditions min. typ. max. unit f scl frequency, scl no wait states - - 400 khz t w(h) pulse duration, scl high 0.6 - - t w(l) pulse duration, scl low 1.3 - - s t r rise time, scl and sda - - 300 ns tf fall time, scl and sda - - 300 ns t setup1 setup time, scl to sda 100 - - ns t hold1 hold time, scl to sda 0 - - ns t (buf) bus free time between stop and start condition 1.3 - - t setup2 setup time, scl to start condition 0.6 - - t hold2 hold time, start condition to scl 0.6 - - t setup3 setup time, scl to stop condition 0.6 - - s c l load capacitance for each bus line - - 400 pf timing characteristics for i 2 c interface signals over recommended operating conditions (unless otherwise noted) figure1. scl and sda timing figure 2. start and stop conditions timing sda t h2 t su2 t (buf) t su3 scl start condition stop condition sda t w(h) t w(l) t su1 t h1 t f t r scl
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 9 reset timing apw7262 symbol parameter test conditions min. typ. max. unit t p(/rst) pulse duration, reset active. no load 100 - - m s t d(i2c_ready) time to enable i 2 c - - 13.5 ms control signal parameters over recommended operating conditions (unless otherwise noted). please refer to recommended use model section on usage of all terminals. figure 3. reset timing reset t d(i2c_ready) t w(reset) i 2 c active i 2 c active
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 10 pin description pin name description a1, a2 vbus charge input voltage. a3 boot supply input for the internal high-side gate driver and an internal level- shift circuit. connect to an external ceramic capacitor and internal diode to create a boosted voltage suitable to drive a logic-level n- channel mosfet. a4 scl i 2 c interface clock. this pin should not be left floating. b1, b2, b3 pmid converter input voltage. connect at least 4.7 m f ceramic capacitor from pvcc to pgnd and place it as close as possible to ic. b4 sda i 2 c interface data. this pin should not be left floating. c1, c2, c3 sw junction point of the internal high-side mosfet source, output filter inductor and internal the low-side mosfet drain. connect the 0.01 m f bootstrap capacitor from sw to boot. c4 stat stat is an open drain output used to indicate the status of the various charger operations. low when charge in progress. stat can be used to drive a led or communicate with a host processor. d1, d2, d3 pgnd power ground. ground connection for high current power converter node. this pin is used as sink for internal low-side gate drivers. d4 otg boost mode enable control pin. when otg actives, the device operates in boost mode. e1 csin positive input of current sensing amplifier for charge terminal. a 0.1 m f ceramic capacitor is placed from csin to csout to provide differential-mode filtering. an optional 0.1 m f ceramic capacitor is placed from csin pin to pgnd for common-mode filtering. e2 cd charge disable. cd=low, charge is enabled, cd=high, charge is disabled. e3 regn supply voltage. this pin provides bias supply, low-side gate drivers and the bootstrap circuit for high-side drivers. ensure that this pin is bypassed by a 1 m f ceramic capacitor next to the pin. e4 csout battery output and negative input of current sensing amplifier for charge terminal. a 0.1 m f ceramic capacitor is placed from csout to csin to provide differential-mode filtering. an optional 0.1 m f ceramic capacitor is placed from csout pin to pgnd for common-mode filtering.
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 11 typical operating characteristics battery voltage, v bat (v) b a t t e r y c h a r g e c u r r e n t ( m a ) battery charge current vs. v bat , v oreg =4.2v, i in_limit =500ma 0 200 400 600 800 1000 2.7 3 3.3 3.6 3.9 4.2 load current, i vbus (ma) otg, load regulation, v bus vs. i vbus 4.8 o u t p u t v o l t a g e , v b u s ( v ) 5.1 4.9 5 5.2 0 100 200 300 400 500 h z _ m o d e c u r r e n t , i v b u s ( u a ) hz_mode current i vbus vs. input voltage v bus with temperature 250 200 150 50 100 0 input voltage, v bus (v) 4 4.4 4.8 5.2 5.6 6 85 c 25 c -30 c no switching quiescent i vbus vs. input voltage v bus with temperature n o s w i t c h i n g c u r r e n t , i v b u s ( m a ) input voltage, v bus (v) 2 2.4 2.6 2.8 3 3.2 2.2 4 4.4 4.8 5.2 5.6 6 85 c 25 c -30 c battery voltage, v bat (v) battery charge current vs. v bat , v oreg =4.2v, i in_limit =100ma b a t t e r y c h a r g e c u r r e n t ( m a ) 0 50 100 150 200 250 2.7 3 3.3 3.6 3.9 4.2 boost mode, no switching quiescent current i bat vs. battery voltage v bat with temperature n o s w i t c h i n g c u r r e n t , i b a t ( u a ) battery voltage, v bat (v) 0 150 200 250 300 350 400 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 100 50 4.3 4.5 85 c 25 c -30 c
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 12 typical operating characteristics battery voltage, v bat (v) h z _ m o d e c u r r e n t , i b a t ( u a ) 10 15 20 25 35 40 boost mode, quiescent current i bat vs. battery voltage v bat in hz_mode with temperature 30 5 0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 85 c 25 c -30 c
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 13 operating waveforms ch1: v bus (5v/div) ch2: v bat (1v/div) ch3: v stat (5v/div) ch4: i bat (500ma/div) time: 1s/div charge mode start-up v bus , v oreg =4.2v, v bat =3.8 1 2 3 4 1 2 3 4 ch1: v bus (5v/div) ch2: i vbus (200ma/div) ch3: v bat (2v/div) ch4: i l (500ma/div) time: 1s/div charge mode start-up v bus , v oreg =4.2v, v bat =3.8, i in_limit =100ma ch1: v bus (5v/div) ch2: i vbus (500ma/div) ch3: v bat (2v/div) ch4: i l (500ma/div) time: 500ms/div charge mode start-up v bus , v oreg =4.2v, v bat =3.8, i in_limit =500ma 1 2 3 4 1 2 3 4 charge mode start-up v bus , v oreg =4.2v, v bat =3.8, i in_limit =800ma ch1: v bus (5v/div) ch2: i vbus (500ma/div) ch3: v bat (2v/div) ch4: i l (1a/div) time: 500ms/div
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 14 operating waveforms charge mode start-up v bus , v oreg =4.2v, v bat =3.8, i in_limit =no limit ch1: v bus (5v/div) ch2: i vbus (500ma/div) ch3: v bat (2v/div) ch4: i l (1a/div) time: 500ms/div 1 2 3 4 charge shutdown with hz_mode bit set, v oreg =4.2v, v bat =3.8, i in_limit =no limit ch1: v stat (5v/div) ch2: i vbus (1a/div) ch3: v bat (2v/div) ch4: i l (1a/div) time: 100ms/div 1 2 3 4 ch1: v stat (5v/div) ch2: i vbus (1a/div) ch3: v bat (2v/div) ch4: i l (1a/div) time: 200 m s/div charge start-up with hz_mode bit reset, v oreg =4.2v, v bat =3.8, i in_limit =no limit 1 2 3 4 charge shutdown with cd pin pulled high, v oreg =4.2v, v bat =float, i in_limit =no limit ch1: v cd (2v/div) ch2: v stat (5v/div) ch3: v bat (2v/div) ch4: i l (1a/div) time: 100ms/div 1 2 3 4
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 15 operating waveforms ch1: v cd (2v/div) ch2: v stat (5v/div) ch3: v bat (2v/div) ch4: il (1a/div) time: 1s/div charge start-up with cd pin pulled low, v oreg =4.2v, v bat =float, i in_limit =no limit 1 2 3 4 battery remove/insertion during charging, v oreg =4.2v, v bat =3.8, i in_limit =no limit, te=0 ch1: i vbus (1a/div) ch2: v bat (2v/div) ch3: i l (1a/div) time: 50ms/div 1 2 3 ch1: i vbus (1a/div) ch2: v bat (2v/div) ch3: i l (1a/div) time: 500ms/div battery remove during charging, v oreg =4.2v, v bat =3.8, i in_limit =no limit, te=1 1 2 3 ch1: v bus (1v/div) ch2: i vbus (1a/div) ch3: v bat (2v/div) ch4: i l (1a/div) time: 5ms/div dpm, v sp =4.533v, v oreg =4.2v, v bat =3.8, i in_limit =no limit, te=1 1 2 3 4
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 16 operating waveforms charge mode, v bus ovp/released ovp, v oreg =4.2v, v bat =3.8, i in_limit =no limit ch1: v bus (2v/div) ch2: v stat (5v/div) ch3: v bat (2v/div) ch4: il (500ma/div) time: 1s/div 1 2 3 4 ch1: v bus (5v/div) ch2: v stat (5v/div) ch3: v bat (2v/div) ch4: il (500ma/div) time: 1s/div charge mode, battery ovp/released ovp, v oreg =4.2v, i in_limit =no limit 1 2 3 4 ch1: v bus (2v/div) ch2: v bat (2v/div) ch3: v stat (5v/div) ch4: i l (1a/div) time: 200 m s/div battery overload, v oreg =4.2v, v bat =float, i in_limit =no limit 1 2 3 4 ch1: v bus (1v/div) ch2: i vbus (1a/div) ch3: v bat (2v/div) ch4: i l (1a/div) time: 20 m s/div dpm, v sp =4.533v, v oreg =4.2v, v bat =3.8, i in_limit =no limit, te=1 (cont.) 1 2 3 4
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 17 operating waveforms otp, v oreg =4.2v, v bat =3.8, i in_limit =no limit, te=1 ch1: v stat (5v/div) ch2: i vbus (1a/div) ch3: v bat (2v/div) ch4: i bat (1a/div) time: 500ms/div 1 2 3 4 ch1: i l (500ma/div) ch2: v lx (5v/div) ch3: v bus (5v/div) time: 500ns/div boost mode, v bat =3.8v, i vbus = no load, in pfm operation 1 2 3 ch1: i l (500ma/div) ch2: v lx (5v/div) ch3: v bus (5v/div) ch4: i vbus (500ma/div) time: 200ns/div boost mode, v bat =3.8v, i vbus = 500ma, in ccm operation 1 2 3 4
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 18 block diagram pwm signal controller sw pgnd regn ugate gate driver gate driver lgate boot regn v regn protection behavior controller i 2 c interface logic control and charge control timer scl sda cd otg vbus charge pump reference and bias v bus v bus v csout pmid v pmid vbus ovp i in_limit v in_dpm v csout v oreg i ocharge csin csout sleep mode v csout +40mv v bus bat ovp v csout v bat_ovp vbus ovp v bus v bus_ovp 3.8v uvlo v bus stat bat short 2v v csout tshut ic t j t shut q1 q2 q3
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 19 typical application circuit vbus pgnd csin sw boot vbat adapter or usb 68m pmid sda scl otg cd stat vaux csout 10k 10k 10k 1uf 4.7uf 1uh 0.01uf 0.1uf 0.1uf pack+ pack- 22uf to system 22uf apw7262 0.1uf regn 1uf
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 20 typical application circuit figure 4. charger vbus por flow chart charger vbus por power on v bus v bus > uvlo n y v bat > v lowv y hz, ce or cd pin=1 y hz state charge configuration state 40 min timer n y n n y hz, ce or cd pin=1 hz state y n charge state reset all resisters, starts 40 min n hz, ce or cd pin=1
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 21 typical application circuit hz state figure 5. hz state flow chart charge configuration state figure 6. charge configuration flow chart hz state y n charge state y hz, cd pin, ce =1 y n cd pin = high n v bat > v lowv charge configuration state 40 min and ce=0 n charge state y
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 22 typical application circuit figure 7. operational flow chart in charge mode charge state in charge state=>charge start figure 8. charger timer flow chart charge start i 2 c writing y n time fault, set ce=1 40 min mode 40 min timeout n y charge state v bat < v short enable i short 30ma, pre- charging y 40 min timeout n timer fault, set ce=1 y charge configuration state fast charge n 40 min timeout y te bit=1 i out < i term v bat > v rech n n stop charging, enable idet sink cuurent for t detect to monitor battery status v bat < v rech y y battery absent, reset charge parameters delay t int charge complete, hz mode v bat < v rech n n y
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 23 function description the apw7262 is a switch-mode battery charger with fixed 3mhz switching frequency, which drives two integrated n-channel power mosfets. the step-down dc/dc con- verter is ideally suited for portable electronic devices. in addition, the apw7262 can supply 5v to usb on-the-go (otg) peripherals through i 2 c programmable. the apw7262 has three operation states in substance: 1.charge state - charges a single-cell li-ion or li-poly- mer battery with an integrated synchronous rectification buck regulator. 2.boost state - supply 5v power to usb-otg with an integrated synchronous rectification boost regulator us- ing battery terminal as input. 3.high-impedance state - both the charging and boost circuits are off. this state consumes low quiescent cur- rent from vbus or the battery. charge mode battery current regulation limits the maximum charging current. using the resistor r sns connected between csin and csout as the bat- tery sensing. input current regulation the total input current is a function of the system supply current and the battery charging current. when the sum- mation of system power and charge power exceeds the maximum vbus input power, the device will reduce input current by using dynamic power management (dpm). using the internal mosfet r ds(on) from vbus to pmid terminal as the input current sensing. charge voltage regulation the regulator is restricted from exceeding this voltage. when the voltage which is across r sns drops below the termination current threshold (i term ), programmed by te bit (reg1[3]) the battery charging is completed. battery charging process while battery voltage is below the v short threshold, the ic applies a constant short-circuit current i short , to the battery. the charge current ramps up to fast charge current, i o(charge) , or a charge current is limited by the input current of i in_limit when the battery voltage is above v short and below v oreg . the input current limit, i in_limit , fast charge current, i o(charge) , and the battery regulation voltage, v oreg , can be set by the host. once the battery voltage reaches v oreg , the charge current is decreased as shown in figure 9. v oreg i short i o_charge v short pre- charge fast charge-current regulation i term voltage regulation v b a t i charge (a) charging process, not limited by i in_limit v oreg i short v short pre- charge fast charge-current regulation i term voltage regulation v b a t i charge (b) charge curve, i in_limit limits i charge figure 9. typical charge process the apw7262 monitors the battery-pack voltage between the csout and pgnd pins as voltage regulation feedback. the regulation voltage is adjustable from 3.5v to 4.44v and is programmed through i 2 c interface. the ic monitors the charging current during the whole voltage regulation phase. the termination current level is programmable by i 2 c interface. the host can set the charge termination bit (reg1[3]) of charge control regis- ter to 0 to disable the charge current termination behavior. when one of the following conditions is occurred, a new charge cycle is initiated. - the battery voltage falls below the v oreg - v rech thresh- old when te bit is set to 0. - vbus power-on reset (por), if battery voltage is below the v lowv threshold.
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 24 function description safety timer at the beginning of charging process, the ic starts a 40- minute timer that can be only disabled by vbus por toggle. when the 40-minute timer times out, the ic turns off the charging operation, set ce bit to 1 (reg1[2]) and indicates a timer fault (110) on the fault bit (reg[2:0]). toggle por or write ce bit to 0 can restart charging process. fault condition is cleared by por and fault sta- tus bits can only be updated after the stat bit are read by the host. in default operation condition, 32-second timer is dis- abled and it can be programmable through 32sec timer bit (reg6[7]). if 32-second timer is enabled, it can be reset by any write-action performed by host through i 2 c interface. writing 1 to reset the tmr_rst bit (reg0[7]) will reset the 32-second timer and tmr_rst is auto- matically set to 0 after the 32-second timer is reset. the charge is terminated and charge parameters are reset to default values when the 32-second timer expires. then the 40-minute timer starts and the charge resumes. special charger the apw7262 has additional functionality to limit input current in case a current-limited special charger is sup- plying vbus. if v bus voltage is equal to the programmable v sp (reg5[4]), the pwm controller starts to decrease the operation frequency and limits the charge current to keep v bus =v sp . safety settings the apw7262 provides a safety register (reg6) to avoid the value of the i o_charge exceeding from the value of the isafe (reg4[6:4]). the isafe register establishes value that limit the maxi- mum value of i o_charge used by the control logic. if the host attempts to write a value higher than isafe to i o_charge , the isafe value as the i o_charge register value. to prevent overheating of the chip during the charging process, the ic monitors the junction temperature, t j , of the die. once t j reaches the thermal regulation threshold, t cf , the ic begins to taper down the charge current. when the junction temperature increases approximately 10 o c above t cf , the charge current is reduced to zero. in any state, the ic suspends charging if t j exceeds t shtdwn . in thermal shutdown mode, pwm is turned off and all timers are frozen. when t j falls below t shtdwn by approxi- mately 10 o c, the apw7262 resumes charging process. during charging process, the apw7262 continuously monitors v bus voltage. if v bus falls below uvlo threshold, the ic stops to charge and sets stat bits to 11 , the fault bits to 011 off. if vbus rises above uvlo rising threshold, the charging process is repeated. input current limit the apw7262 integrated the input current sensing circuit and control loop. when operating in boost mode, the in- put current limit is default 500ma. in charge mode, the input current limit is set by the programmed control bits in register 01h. thermal regulation if the v bus voltage falls below the sleep mode entry threshold, v csout +v slp , the ic enters to the sleep mode. this feature prevents draining the battery during the ab- sence of vbus. during sleep mode, the internal reverse blocking switch and pwm controller are turned off. sleep mode vbus low voltage detection (uvlo) the ic provides a built-in input over voltage protection (ovp) to protect the device and other components against damage if the vbus voltage goes too high. when the vbus ovp condition is detected, the ic turns off the pwm converter, sets the stat bit to 11 and fault bits to 001 . once vbus drops below the vbus ovp exit threshold, the fault is cleared and charge process resumes. vbus over-voltage protection the ic provides a built-in over voltage protection to pro- tect the device and other components against damage if the battery voltage goes too high, as when the battery is suddenly removed. when the battery ovp condition is detected, the ic turns off the pwm converter, sets the stat bit to 11 and fault bits to 100 . once v bat drops to the battery ovp threshold, the fault is cleared and charge process resumes. battery over-voltage protection
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 25 if the battery voltage v bat is below the short circuit thresh- old v short , a constant current source i short supplies v bat until v bat > v short . battery short circuit protection function description the apw7262 monitors internal high-side mosfet for current sensing. if the peak current exceeds the high- side mosfet limit threshold, it will turn off the high-side mosfet until the next cycle. when the current is below the over-current threshold, the high-side driver automati- cally resumes. cycle-by-cycle charge mode current limit boost mode can be enabled if otg pin and opa_mode bits as indicated in below table. boost mode otg_en otg pin otg_pl opa_mode boost 1 high 1 x enable 1 low 0 x enable x x x 1 enable 1 high 0 0 disable 1 low 1 0 disable 0 x x 0 disable the apw7262 operates in boost mode and delivers power to vbus from the battery. in normal boost mode, the apw7262 converts the battery voltage (2.5v to 4.5v) to vbus (5v) and delivers a current ibo 500ma at lowest to support other usb otg devices connected to the usb connector. in boost mode, the apw7262 provides an integrated, fixed 3-mhz frequency voltage-mode controller to regulate out- put voltage vbus as the same as charge mode operation. in boost mode, cycle-by-cycle current limit is sensed through the r sns from csin to csout. the peak current limit threshold is equal to (0.12v/r sns ). for example, if r sns =68m w, the peak current limit is about 1.76a. when current limit event is triggered, ic will turn off q3 driver. if current limit event is released, it will re-back normal operation. pwm controller in boost mode in boost mode, under light load conditions, the ic oper- ates in pfm mode (power saving) to reduce the power loss and improve the converter efficiency. in pfm mode, the on-time pulse width is constant and regulates off-time by zero crossing sensing. pfm mode at light load the ic provides a built-in over voltage protection to pro- tect the device and other components against damage if the v bus voltage goes too high. when the vbus ovp con- dition is detected, the ic turns off the pwm converter, sets the stat bit to 11 , fault bits to 001 and resets opa_mode bit to 0. and then, apw7262 will return to charge mode. vbus over-voltage protection in boost mode, the ic provides a built-in input over volt- age protection to protect the device and other compo- nents against damage if the vbat voltage goes too high. when the vbat ovp condition is detected, the ic turns off the pwm converter, sets the stat bit to 11 and resets opa_mode bit to 0. and then, apw7262 will return to charge mode. battery over-voltage protection
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 26 i 2 c introduction i 2 c serial control interface the apw7262 dap has a bidirectional i 2 c interface that compatible with the i 2 c (inter ic) bus protocol and supports standard mode (100-khz), fast mode (400-khz) and the high-speed mode (up to 3.4mbps in wire mode) data transfer rates for single byte write and read operations. this is a slave only device that does not support a multi- master bus environment or wait state insertion. the control interface is used to program the registers of the device and to read device status. the dap supports the standard-mode i 2 c bus operation (100 khz maximum), the fast i 2 c bus operation (400 khz maximum) and the high-speed mode (up to 3.4mbps in wire mode). the dap performs all i2c operations without i 2 c wait cycles. general i 2 c operation the i 2 c bus uses two signals; sda (data) and scl (clock), to communicate between integrated circuits in a system. data is transferred on the bus serially one bit at a time. the address and data can be transferred in byte (8-bit) format, with the most significant bit (msb) transferred first. in addition, each byte transferred on the bus is acknowl- edged by the receiving device with an acknowledge bit. each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. the bus uses transitions on the data pin (sda) while the clock is high to indicate a start and stop conditions. a high- to-low transition on sda indicates a start and a low-to-high transition indicates a stop. normal data bit transitions must occur within the low time of the clock period. these conditions are shown in figure 10. the master generates the 7-bit slave address and the read/write (r/w) bit to open communication with another device and then waits for an acknowledge condition. the apw7262 holds sda low during the acknowledge clock period to indicate an acknowledgment. when this occurs, the master transmits the next byte of the sequence. each device is addressed by a unique 7-bit slave address plus r/w bit (1 byte). all compatible devices share the same signals via a bidirectional bus using a wired-and connection. an external pull-up resistor must be used for the sda and scl signals to set the high level for the bus. figure 10. typical i 2 c sequence there is no limit on the number of bytes that can be transmitted between start and stop conditions. when the last word transfers, the master generates a stop condition to release the bus. a generic data transfer sequence is shown in figure 10. pin a_sel defines the i 2 c device address. the device 7-bit address is defined as 1101010 (6ah) for apw7262. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7-bit slave address r/ w a 8-bit register address (n) 8-bit register data for address (n) a a a 8-bit register data for address (n) sda scl start stop
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 27 i 2 c introduction single-byte transfer the serial control interface supports single-byte read/write operations for sub-addresses 0x00 to 0xff. supplying a sub-address for each sub-address transaction is referred to as random i 2 c addressing. the apw7262 also supports sequential i 2 c addressing. for write transactions, if a sub-address is issued followed by data for that sub-address and the 15 sub-addresses that follow, a sequential i 2 c write transaction has taken place, and the data for all 16 sub-addresses is successfully received by the apw7262. for i 2 c sequential write transactions, the sub- address then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many sub-addresses are written. as was true for random addressing, sequential addressing requires that a complete set of data be transmitted. if only a partial set of data is written to the last sub- address, the data for the last sub-address is discarded. however, all other data written is accepted; only the incomplete data is discarded. single-byte write as shown in figure 11, a single-byte data write transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the read/write bit. the read/write bit determines the direction of the data transfer. for a write data transfer, the read/write bit will be a 0. after receiving the correct i 2 c device address and the read/write bit, the dap responds with an acknowledge bit. next, the master transmits the address byte or bytes corresponding to the apw7262 internal memory address being accessed. after receiving the address byte, the apw7262 again responds with an acknowledge bit. next, the master device transmits the data byte to be written to the memory address being accessed. after receiving the data byte, the apw7262 again responds with an acknowl- edge bit. finally, the master device transmits a stop condition to complete the single-byte data write transfer. figure 11. single-byte write transfer single-byte read as shown in figure 12, a single-byte data read transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the read/write bit. for the data read transfer, both a write followed by a read are actually done. initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. as a result, the read/write bit becomes a 0. after receiving the apw7262 address and the read/write bit, apw7262 responds with an acknowledge bit. in addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the apw7262 address and the read/write bit again. this time the read/write bit becomes a 1, indicating a read transfer. after receiving the address and the read/write bit, the apw7262 again responds with an acknowledge bit. next, the apw7262 transmits the data byte from the memory address being read. after receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. a6 a5 a4 a3 a2 a1 a0 ack r/w a6 a5 a4 a3 a2 a1 a0 ack a7 d6 d5 d4 d3 d2 d1 d0 ack d7 start condition stop condition i 2 c device address and read/ write bit sub-address data byte acknowledge acknowledge acknowledge
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 28 i 2 c introduction register description the apw7262 has seven user-accessible registers. it is as defined as below table. single-byte read (cont.) figure 12. single-byte read transfer register address name read/write/read only state default value 00 control/status read/write x1xx 0xxx 01 control/input current limit read/write 0111 0000 02 control/battery voltage read/write 0000 1010 03 vender/part/revision read only 010x xxxx 04 termination/fast charge current read/write 0000 0001 05 enable/special charger voltage read/write/read only 001x x100 06 safety limit read/write 1100 0000 the below tables define the operation of each register bit. default values are in bold text. table1. register address: 00 bit name data read/write description write write 0 or 1 has no effect 7 tmr_rst/otg read otg pin status. 0 => otg=low; 1 => otg=high 0 read/write disable stat pin function 6 en_stat 1 read/write enable stat pin function 00 read ready 01 read charge in process 10 read charge done [5:4] stat 11 read fault 0 read not in boost mode 3 boost 1 read in boost mode 000 read charge mode : normal boost mode : normal 001 read charge mode : vbus ovp boost mode : vbus ovp 010 read charge mode : sleep mode boost mode : over load [2:0] fault 011 read charge mode : vbus < uvlo boost mode : vbat < uvlo bst a6 a5 a1 a0 ack r/w a6 a1 a0 ack a7 start condition stop condition i 2 c device address and read/ write bit sub-address acknowledge acknowledge a6 a5 a1 a0 r/w i 2 c device address and read/ write bit ack d6 d1 d0 ack d7 data byte acknowledge not acknowledge repeat start condition
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 29 register description table2. register address: 01 bit name data read/write description 100 read charge mode : battery ovp boost mode : n/a 101 read charge mode : thermal shutdown boost mode : thermal shutdown 110 read charge mode : timer fault boost mode : timer fault [2:0] fault 111 read charge mode : no battery boost mode : n/a bit name data read/write description 00 read/write 100ma 01 read/write 500ma 10 read/write 800ma [7:6] i in_limit 11 read/write no current limit 00 read/write 3.4v 01 read/write 3.5v 10 read/write 3.6v [5:4] v lowv 11 read/write 3.7v 0 read/write disable charge current termination 3 te 1 read/write enable charge current termination 0 read/write charge enabled 2 ce 1 read/write charge disabled 0 read/write not high-impedance mode 1 hz_mode 1 read/write high-impedance mode 0 read/write charge mode 0 opa_mode 1 read/write boost mode
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 30 register description table3. register address: 02 bit name data read/write description 000000 read/write 3.5v 000001 read/write 3.52v 000010 read/write 3.54v 000011 read/write 3.56v 000100 read/write 3.58v 000101 read/write 3.6v 000110 read/write 3.62v 000111 read/write 3.64v 001000 read/write 3.66v 001001 read/write 3.68v 001010 read/write 3.7v 001011 read/write 3.72v 001100 read/write 3.74v 001101 read/write 3.76v 001110 read/write 3.78v 001111 read/write 3.8v 010000 read/write 3.82v 010001 read/write 3.84v 010010 read/write 3.86v 010011 read/write 3.88v 010100 read/write 3.9v 010101 read/write 3.92v 010110 read/write 3.94v 010111 read/write 3.96v 011000 read/write 3.98v 011001 read/write 4v 011010 read/write 4.02v 011011 read/write 4.04v 011100 read/write 4.06v 011101 read/write 4.08v 011110 read/write 4.1v 011111 read/write 4.12v 100000 read/write 4.14v 100001 read/write 4.16v 100010 read/write 4.18v 100011 read/write 4.2v [7:2] oreg 100100 read/write 4.22v
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 31 register description table3. register address: 02 bit name data read/write description 100100 read/write 4.22v 100101 read/write 4.24v 100110 read/write 4.26v 100111 read/write 4.28v 101000 read/write 4.3v 101001 read/write 4.32v 101010 read/write 4.34v 101011 read/write 4.36v 101100 read/write 4.38v 101101 read/write 4.4v 101110 read/write 4.42v 101111 read/write 4.44v 110000 read/write 4.44v 110001 read/write 4.44v 110010 read/write 4.44v 110011 read/write 4.44v 110100 read/write 4.44v 110101 read/write 4.44v 110110 read/write 4.44v 110111 read/write 4.44v 111000 read/write 4.44v 111001 read/write 4.44v 111010 read/write 4.44v 111011 read/write 4.44v 111100 read/write 4.44v 111101 read/write 4.44v [7:2] oreg 111110 read/write 4.44v 0 read/write otg pin active low 1 otg_pl 1 read/write otg pin active high 0 read/write otg pin is disabled 0 otg_en 1 read/write otg pin is enabled
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 32 register description table4. register address: 03 bit name data read/write description [7:5] vender code 010 read only [4:3] pn xx read only for i 2 c address [2:0] rev xxx read only ic revision table5. register address: 04 bit name data read/write description 7 reserved 0 read only unused 000 read/write r sns : 56m w =>668ma; r sns : 68m w =>550ma ; r sns : 100m w =>374ma 001 read/write r sns : 56m w =>789ma ; r sns : 68m w =>650ma ; r sns : 100m w =>442ma 010 read/write r sns : 56m w =>911ma ; r sns : 68m w =>750ma ; r sns : 100m w =>510ma 011 read/write r sns : 56m w =>1032ma ; r sns : 68m w =>850ma ; r sns : 100m w =>578ma 100 read/write r sns :56m w =>1275ma ; r sns : 68m w =>1050ma ; r sns : 100m w =>714ma 101 read/write r sns : 56m w =>1396ma ; r sns : 68m w =>1150ma ; r sns : 100m w =>782ma 110 read/write r sns : 56m w =>1639ma ; r sns : 68m w =>1350ma ; r sns : 100m w =>918ma [6:4] iocharge 111 read/write r sns :56m w =>1882ma ; r sns : 68m w =>1550ma ; r sns : 100m w =>1054ma 3 reserved 0 read only unused 000 read/write r sns : 56m w =>59ma ; r sns : 68m w =>49ma ; r sns : 100m w =>33ma 001 read/write r sns : 56m w =>118ma ; r sns : 68m w =>97ma ; r sns : 100m w =>66ma 010 read/write r sns : 56m w =>177ma ; r sns : 68m w =>146ma ; r sns : 100m w =>99ma 011 read/write r sns : 56m w =>236ma ; r sns : 68m w =>194ma ; r sns : 100m w =>132ma 100 read/write r sns : 56m w =>295ma ; r sns : 68m w =>243ma ; r sns : 100m w =>165ma 101 read/write r sns : 56m w =>353ma ; r sns : 68m w =>291ma ; r sns : 100m w =>198ma 110 read/write r sns : 56m w =>412ma ; r sns : 68m w =>340ma ; r sns : 100m w =>231ma [2:0] iterm 111 read/write r sns : 56m w =>471ma ; r sns : 68m w =>388ma ; r sns : 100m w =>264ma
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 33 register description table6. register address: 05 table7. register address: 06 bit name data read/write description 0 call out 32sec timer function 7 timer 1 read/write no 32sec timer function 000 read/write r sns : 56m w =>668ma ; r sns : 68m w =>550ma ; r sns : 100m w =>374ma 001 read/write r sns : 56m w =>789ma ; r sns : 68m w =>650ma ; r sns : 100m w =>442ma 010 read/write r sns : 56m w =>911ma ; r sns : 68m w =>750ma ; r sns : 100m w =>510ma 011 read/write r sns : 56m w =>1032ma ; r sns : 68m w =>850ma ; r sns : 100m w =>578ma 100 read/write r sns : 56m w =>1275ma ; r sns : 68m w =>1050ma ; r sns : 100m w =>714ma 101 read/write r sns : 56m w =>1396ma ; r sns : 68m w =>1150ma ; r sns : 100m w =>782ma 110 read/write r sns : 56m w =>1639ma ; r sns : 68m w =>1350ma ; r sns : 100m w =>918ma [6:4] isafe 111 read/write r sns : 56m w =>1882ma ; r sns : 68m w =>1550ma ; r sns : 100m w =>1054ma bit name data read/write description 7 reserved 0 read only unused 6 reserved 0 read/write unused 0 read/write charge current is controlled by i ocharge bits 5 io_level 1 read/write charge current is set to 395ma for r sns : 56m w , 325ma for r sns : 68m w , 221ma for r sns : 100m w 0 read only special charger is not active 4 sp 1 read only special charger is active and v bus is being regulated to v sp 0 read only cd pin is low 3 en_level 1 read only cd pin is high 000 read/write v sp =4.213v 001 read/write v sp =4.29v 010 read/write v sp =4.373v 011 read/write v sp =4.453v 100 read/write v sp =4.533v 101 read/write v sp =4.613v 110 read/write v sp =4.693v [2:0] vsp 111 read/write v sp =4.773v
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 34 register description table6. register address: 06 (cont.) [3:0] vsafe 0000 read/write 4.2v 0001 read/write 4.22v 0010 read/write 4.24v 0011 read/write 4.26v 0100 read/write 4.28v 0101 read/write 4.3v 0110 read/write 4.32v 0111 read/write 4.34v 1000 read/write 4.36v 1001 read/write 4.38v 1010 read/write 4.4v 1011 read/write 4.42v 1100 read/write 4.44v 1101 read/write 4.44v 1110 read/write 4.44v 1111 read/write 4.44v
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 35 package information wlcsp1.7x2.1-20 pin 1 e d aaa a1 a2 a nx c seating plane e e b e / 2 s y m b o l min. max. 0.63 0.19 0.20 0.30 2.10 2.22 0.23 a a1 b d e e millimeters a2 0.32 0.40 0.40 bsc wlcsp1.7x2.1-20 0.016 bsc min. max. inches 0.025 0.007 0.013 0.016 0.008 0.012 0.083 0.087 0.009 1.70 1.98 0.067 0.078 aaa 0.05 0.002
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 36 package information tqfn4x4-20a pin 1 e d aaa a nx c e a1 a3 d2 e 2 pin 1 corner e l k k 0.20 0.008 3.90 4.10 0.154 0.161 3.90 4.10 0.154 0.161 aaa 0.08 0.003 0.70 0.098 0.028 0.002 0.50 bsc 0.020 bsc s y m b o l min. max. 0.80 0.00 0.18 0.30 2.00 2.50 0.05 2.00 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tqfn4x4-20a 0.35 0.45 2.50 0.008 ref min. max. inches 0.031 0.000 0.008 0.012 0.079 0.098 0.079 0.014 0.018 note : 1. followed from jedec mo-220 vggd-5.
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 37 application a h t1 c d d w e1 f 178.0 2.00 50 min. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 min. 20.2 min. 8.0 0.30 1.75 0.10 3.5 0.05 p0 p1 p2 d0 d1 t a0 b0 k0 wlcsp 1.7x2.1-20 4.0 0.10 4.0 0.10 2.0 0.05 1.5+0.10 -0.00 1.5 min. 0.6+0.00 -0.40 2.15 0.05 2.32 0.05 0.81 0.05 a h t1 c d d w e1 f 330.0 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 -0.20 1.5 min. 20.2 min. 12.0 0.30 1.75 0.10 5.5 0.05 p0 p1 p2 d0 d1 t a0 b0 k0 tqfn4x4-20a 4.0 0.10 8.0 0.10 2.0 0.05 1.5+0.10 -0.00 1.5 min. 0.6+0.00 -0.40 4.30 0.20 4.30 0.20 1.00 0.20 (mm) carrier tape & reel dimensions a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d devices per unit package type unit quantity wlcsp1.7x2.1-20 tape & reel 3000 tqfn4x4-20a tape & reel 3000
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 38 user direction of feed taping direction information wlcsp1.7x2.1-20 tqfn4x4-20a user direction of feed
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 39 classification profile
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 40 classification reflow profiles profile feature sn-pb eutectic assembly pb-free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) (t s ) 100 c 150 c 60-120 seconds 150 c 200 c 60-120 seconds average ramp-up rate (t smax to t p ) 3 c/second max. 3 c/second max. liquidous temperature (t l ) time at liquidous (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak package body temperature (t p )* see classification temp in table 1 see classification temp in table 2 time (t p )** within 5 c of the specified classification temperature (t c ) 20** seconds 30** seconds average ramp-down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb-free process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm C 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 220 c 3 2.5 mm 220 c 220 c test item method description solderability jesd-22, b102 5 sec, 245 c holt jesd-22, a108 1000 hrs, bias @ tj=125 c pct jesd-22, a102 168 hrs, 100 % rh, 2atm, 121 c tct jesd-22, a104 500 cycles, -65 c~150 c hbm mil-std-883-3015.7 vhbm R 2kv mm jesd-22, a115 vmm R 200v latch-up jesd 78 10ms, 1 tr R 100ma reliability test program
copyright ? anpec electronics corp. rev. a.3 - mar., 2016 apw7262 www.anpec.com.tw 41 customer service anpec electronics corp. head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 2f, no. 11, lane 218, sec 2 jhongsing rd., sindian city, taipei county 23146, taiwan tel : 886-2-2910-3838 fax : 886-2-2917-3838

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